In recent years, demands for miniaturizing semiconductor devices have been increasing along with the increase in the degree of integration, functionality and speed thereof. In view of this, various device structures have been proposed in the art, aiming at the reduction in the area of the substrate taken up by transistors. Among others, attention has been drawn to field effect transistors having a fin-shaped structure. A field effect transistors having the fin-shaped structure is commonly called a fin-shaped FET (field effect transistor), and has an active region including thin wall (fin)-like semiconductor regions perpendicular to the principle plane of the substrate. In a fin-shaped FET, the side surface of the semiconductor region can be used as a channel surface, whereby it is possible to reduce the area on the substrate taken up by the transistor (see, for example, Patent Document 1 and Non-Patent Document 1).
FIG. 16A to FIG. 16D show a structure of a conventional fin-shaped FET, wherein FIG. 16A is a plan view of the device, FIG. 16B is a cross-sectional view taken along line A-A in FIG. 16A, FIG. 16C is a cross-sectional view taken along line B-B in FIG. 16A, and FIG. 16D is a cross-sectional view taken along line C-C in FIG. 16A.
As shown in FIG. 16A to FIG. 16D, a conventional fin-shaped FET includes a supporting substrate 101 made of silicon, an insulating layer 102 made of silicon oxide formed on the supporting substrate 101, semiconductor regions 103a to 103d each formed into a fin shape on the insulating layer 102 (hereinafter referred to as the “fin-shaped semiconductor regions”), a gate electrode 105 formed on the fin-shaped semiconductor regions 103a to 103d via gate insulating films 104a to 104d, insulative sidewall spacers 106 formed on side surfaces of the gate electrode 105, extension regions 107 formed on opposite side regions of the fin-shaped semiconductor regions 103a to 103d sandwiching the gate electrode 105 therebetween, and source-drain regions 117 formed on opposite side regions of the fin-shaped semiconductor regions 103a to 103d sandwiching the gate electrode 105 and the insulative sidewall spacer 106 therebetween. The fin-shaped semiconductor regions 103a to 103d are placed on the insulating layer 102 so as to be arranged at regular intervals in the gate width direction. The gate electrode 105 is formed so as to extend across the fin-shaped semiconductor regions 103a to 103d in the gate width direction. The extension region 107 includes a first impurity region 107a formed in an upper portion of each of the fin-shaped semiconductor regions 103a to 103d, and a second impurity region 107b formed in a side portion of each of the fin-shaped semiconductor regions 103a to 103d. The source-drain region 117 includes a third impurity region 117a formed in an upper portion of each of the fin-shaped semiconductor regions 103a to 103d, and a fourth impurity region 117b formed in a side portion of each of the fin-shaped semiconductor regions 103a to 103d. Note that pocket regions are not described herein or shown in the figure.
FIG. 17A to FIG. 17D are cross-sectional views, showing, step by step, a conventional method for producing a semiconductor device. Note that FIG. 17A to FIG. 17D correspond to the cross-sectional structure taken along line C-C in FIG. 16A. In FIG. 17A to FIG. 17D, like elements to those shown in FIG. 16A to FIG. 16D are denoted by like reference numerals and will not be described again.
First, as shown in FIG. 17A, there is provided an SOI (silicon on insulator) substrate, in which the insulating layer 102 made of silicon oxide is provided on the supporting substrate 101 made of silicon, and a semiconductor layer made of silicon is provided on the insulating layer 102. Then, the semiconductor layer is patterned to form the fin-shaped semiconductor region 103b to be the active region.
Then, as shown in FIG. 17B, the gate insulating film 104 is formed on the surface of the fin-shaped semiconductor region 103b, after which a polysilicon film 105A is formed across the entire surface of the supporting substrate 102.
Then, as shown in FIG. 17C, the polysilicon film 105A and the gate insulating film 104 are etched successively to form the gate electrode 105 on the fin-shaped semiconductor region 103b with the gate insulating film 104b interposed therebetween. Then, using the gate electrode 105 as a mask, the semiconductor region 103b is ion-implanted with an impurity to form the extension region 107 and the pocket region (not shown).
Next, as shown in FIG. 17D, an insulating film is formed across the entire surface of the supporting substrate 102, and then the insulating film is etched back by using anisotropic dry etching to thereby form the insulative sidewall spacer 106 on the side surface of the gate electrode 105. Then, using the gate electrode 105 and the side wall 106 as a mask, the semiconductor region 103b is ion-implanted with an impurity to form the source-drain region 117.
Through the steps described above, it is possible to obtain a fin-shaped MISFET (metal insulator semiconductor field effect transistor) having the gate electrode 105 formed on the fin-shaped semiconductor region 103b with the gate insulating film 104b interposed therebetween.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2006-196821
[Non-Patent Document 1] D. Lenoble, et al., Enhanced performance of PMOS MUGFET via integration of conformal plasma-doped source/drain extensions, 2006 Symposium on VLSI Technology Digest of Technical Papers, p. 212